1. Field of the Invention
The present invention relates to a film forming method and film forming apparatus, which form a seed film and a thin film on a surface of an object to be processed, such as a semiconductor wafer.
2. Description of the Related Art
Generally, in order to manufacture a semiconductor integrated circuit, various processes, such as a film forming process, an etching process, an oxidation process, a diffusion process, a modification process, and a natural oxide film removing process, are performed on a semiconductor wafer including a silicon substrate, etc. The film forming process is described as an example from among the various processes. For example, while manufacturing a semiconductor integrated circuit, such as a dynamic random access memory (DRAM), the film forming process may be performed by providing a recessed portion, such as contact hole, a through hole, a wire groove, or a cylinder groove of a capacitor having a cylindrical structure, on an insulation film formed on a surface of a semiconductor wafer, and embedding the recessed portion with a conductive thin film.
For example, a silicon film containing impurities has been conventionally used as a thin film for embedding the recessed portion, as the silicon film has relatively satisfactory step coverage and furthermore, is relatively inexpensive. The embedding of the recessed portion will now be described with reference to FIGS. 19A and 19B. FIGS. 19A and 19B are views showing an example embedding the recessed portion provided on the surface of the semiconductor wafer.
As shown in FIG. 19A, an insulation film 2 as a base formed of, for example, SiO2, is thinly formed on a surface of a semiconductor wafer W (hereinafter, also referred to as a wafer W) including, for example, a silicon substrate as an object to be processed, and a recessed portion 4 is provided on the insulation film 2. The recessed portion 4 is equivalent to a contact hole promoting contact with a bottom layer or a substrate itself, a through hole, a wire groove, a cylinder groove of a capacitor having a cylindrical structure, or the like. In FIG. 19A, a contact hole promoting contact with a substrate itself is shown as an example. Also, as shown in FIG. 19B, a conductive thin film 6 is formed on the surface of the semiconductor wafer W to embed the recessed portion 4. The silicon film containing impurities as described above is widely used as the thin film 6.
As a film forming method for forming the thin film 6, a film forming method (Patent Reference 1) where a single crystal thin film including impurities is formed at a range of low pressure from about 1 to about 10−6 Pa by supplying, for example, a gas including a component element of semiconductor silicon, such as SiCl4, and a gas including an impurity element, such as BCl3, alternately into a processing container, a film forming method (Patent Reference 2) where, for example, forming of a polysilicon layer by supplying a monosilane (SiH4) gas and forming of a phosphorous adsorption layer by supplying a phosphine gas are alternately performed, and a method (Patent Reference 3) of forming a film via chemical vapor deposition (CVD) by simultaneously supplying monosilane and boron trichloride (BCl3) are known.
In the above-described film forming methods, step coverage is satisfactory and an embedding characteristic is excellent since the recessed portion described above is satisfactorily embedded when a design rule is relatively loose since a request for minuteness is not so strict. However, when the design rule is strict due to a recent increased request for further minuteness, a sufficient embedding characteristic may not be obtained. Also, for example, the existence of a void 8 generated in the film as shown in FIG. 19B cannot be ignored. The void 8 is a cause for increasing contact resistance.
Specifically, recently, a strict design rule where the recessed portion 4 described above has a hole diameter less than or equal to 40 nm and an aspect ratio is equal to or higher than 10 has been requested, and thus the above problems need to be solved early. Also, aside from the generation of the void 8, a precision of surface roughness may also decrease.
3. Prior Art Reference
(Patent Reference 1) Japanese Laid-Open Patent Publication No. sho 61-034928
(Patent Reference 2) Japanese Laid-Open Patent Publication No. hei 05-251357
(Patent Reference 3) Japanese Laid-Open Patent Publication No. hei 08-153688